Tensilica

　Tensilica is a fast growing company focused on providing the ultimate in application-specific microprocessor solutions for use in today's high-volume embedded systems. Tensilica was incorporated in July of 1997 by key managers and executives with four key technical disciplines: microprocessor architecture, ASIC and VLSI design, advanced software development, and Electronic Design Automation (EDA). The groups’ goal was to create the world's first truly configurable and extensible microprocessor architecture and the support environment that could enable embedded system designers to build better, more highly integrated SOCs in less time.
　The company has an experienced management team and a world class technical team with the support and backing of industry veterans and technical advisors. The company is backed by three leading venture capital firms: Oak Investment Partners, Worldview Technology Partners, and Foundation Capital, as well as five industry leading strategic investors: Cisco Systems, Inc., Matsushita Electric Industrial Company Ltd., Altera Corporation, NEC Corporation and Conexant Systems.
　Tensilica began working with early customers in the last half of 1998 and publicly released its flagship Xtensa configurable, extensible processor product line in February of 1999.
For more details on our company, see our Corporate Profile.

Products－

The Xtensa Processor

Download the Product Brief (pdf).
Japanese Version (PDF) Chinese Version (PDF)　 Korean Version (PDF)
Download the Xtensa Architecture White Paper (PDF)

　A configurable, extensible and synthesizable processor core, Tensilica’s Xtensa processor is the first microprocessor architecture designed specifically to address embedded System-On-Chip (SOC) applications. It was designed from the start to be a configurable architecture enabling designers to tailor each implementation to match the application requirements for the target SOC.
The Xtensa processor is unlike any other conventional embedded processor core – it changes the rules of the SOC game. Using Xtensa technology, the system designer molds the processor to fit the application by selecting and configuring predefined elements of the architecture and by inventing completely new instructions and hardware execution units that can deliver performance levels orders of magnitude faster than alternative solutions. The Xtensa Processor Generator also automatically generates a complete optimized software environment – including operating system support – for each processor configuration. The power and flexibility of the configurable Xtensa processor make it the ideal choice for all complex SOC designs.

　To learn more details about the Xtensa Processor solution - the Xtensa architecture and the comprehensive software and design methodology support for the Xtensa core - click About Xtensa.

Take a Test Drive

After you’ve browsed the web site and taken the About Xtensa guided tour, explore the Xtensa Processor Generator in more detail by taking a Test Drive.

Changing SOC Design: Designing With
Processors Instead of RTL

Conventional wisdom says that processors - both traditional microprocessors as well as traditional digital signal processors (DSPs) - are general purpose engines that are fine for low performance task but lack the horsepower needed to tackle leading edge design challenges. Thus for most SOC designers, conventional wisdom says one processor in the corner of a die is all that is needed for most SOCs and the rest is designed as pure hardwired logic using traditional register transfer level (RTL) design methodologies.

Tensilica licensees have learned that the conventional wisdom is wrong. Configurable processors allow Tensilica licensees to implement functions using Xtensa processors that once could only be done in RTL. SOCs can now be designed in far less time, with far less risk, and with dramatically lower verification effort.

With over 60 licensees including some of the biggest names in the consumer and communications markets using Tensilica technology and using an average of more than five Xtensa processors per IC, shouldn㦙 you learn more about designing with processors instead of gates, and the power of configurable processors to change the way you approach SOC design? See how you can speed RTL design.

Xtensa Processor Core Peformance Summary
Xtensa Processor Architecture	5-stage high-performance pipeline 32-bit standard register widths and ALU User-defined registers and execution datapaths up to 1024 bits
Instruction Set	Xtensa ISA - Patented Compact 16/24b native instruction coding (no mode switch) delivers unsurpassed code density with no performance penalty
Clock Speed	200 MHz in 0.18 micron process (worst case conditions) 300-350 MHz in 0.13 micron process (worst case conditions)
Performance	Base architecture outperforms the leading brand of processor core TIE (Tensilica Instruction Extensions) delivers 5X, 10X, 100X+ performance increase compared to the leading brand
Size	Approximately 25,000 gates - base processor
Power Consumption	0.4 mW/MHz in 0.18 micron process at 1.8V 0.1 mW/MHz in 0.13 micron process at 0.9V

Clock speed, size/area, power consumption and application performance vary with user choice of configuration options, user-defined TIE extensions, and choice of implementation technology.

Download the Xtensa Processor Overview Handbook (pdf)

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The Xtensa Processor

Xtensa Processor Core Peformance Summary