There are two models of System Explorer hardware products: the MP3CF and MP4CF. Both products enable a block-based prototyping methodology in which the user builds up a reconfigurable prototype of their system using state-of-the art FPGAs and other system components. The System Explorer MP3CF is particularly suited for providing maximum performance in the implementation of pipe-lined data-flow type designs and has been widely adopted as the platform for verifying digital wireless systems. The architecture of the System Explorer MP4CF addresses designs with more complex data paths, such as networking and multimedia systems.

　Aptix provides a suite of software tools for implementation and verification of users designs on the MP3CF and MP4CF platforms. The Logic AggreGATErTM interactive hierarchical partitioning tool enables mapping of netlists into FPGAs and other system components following the natural block-level structure of the design. Explorer software maps the partitioned netlist into the MP3CF/MP4CF platform, configures the prototype, and provides automated hardware debugging tools. The Module Verification Platform (MVP), delivered through Prototype Verification Services, confirms accurate mapping of the netlist to the prototype and enables running regression suites and co-simulation with the major logic simulators.

　The System Explorer product family is built upon on two key proprietary technologies: the Field Programmable Circuit Board (FPCB) and the Field Programmable Interconnect Component (FPIC).The FPCB provides programmable interconnect routing between design blocks. The FPCB employs a plug-and-play modular approach in which system design blocks are represented by components on daughter cards which plug into "free-hole" areas on the FPCB. Programmable routing is accomplished by having all the free-hole connection points pre-routed to a set of the Company's proprietary, high pin count FPICs. FPICs are 1024 pin devices that can route any component I/O to any other I/O. These two principal technologies are protected by a set of over 25 patents.

　The plug-and-play concept provides flexibility to the user to prototype with any required component. It provides Aptix the flexibility to upgrade the rated capacities and speeds of the systems as new FPGAs are introduced and supported. By using the largest and fastest FPGAs, the Company's customers are able to prototype their designs using fewer components, and at a resulting lower cost. With FPGAs now outperforming design creation tools, customers can employ the block-based methodology to implement prototype designs faster. The high pin count FPIC enables the routing between prototyping components to be accomplished with minimal prototyping system delays. This maximizes the actual operating speed of the prototyping system.

　Aptix products take system level structural descriptions and gate-level ASIC netlists and map system elements into standard components and the ASIC design custom logic into FPGAs, as guided by the designer. For system-on-chip (SoC) designs, IP blocks can be represented as bonded-out silicon or mapped into FPGAs. The FPGA vendor tools for placement and routing of the FPGAs are driven through the Aptix software, thereby enhancing the ease-of-use and system compilation time. The Aptix software generates prototype programming data which is downloaded to the prototyping system. The Aptix software also controls interfaces to debugging tools, such as logic analyzers.
The working prototype of a system or ASIC is created by using modules with pre-mounted components, such as FPGAs, which plug directly into the FPCB open-hole pattern to represent all the elements of the design. These modules automatically pick up power, ground and programming pins from pre-routed circuits on the FPCB, making it a truly plug-and-play system. This method makes it quicker to prototype a system with fewer errors and gives the product an ease-of-use advantage.

　The System Explorer products have a direct-connect high-speed bus, which is important for many real-time applications to get data quickly between components that must run at a minimum threshold speed to process information correctly. Data communication applications are particularly sensitive to this issue, as they cannot usually be slowed down and must process data at a very fast rate. In this scenario, the data rate between components would be confined to the System Explorer high speed bus (up to 50 MHz) and the rest of the system not in this critical path would transfer data up to about 35 MHz through the FPIC devices.