Stratix Devices: New Levels of System Integration
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Altera's flagship device family, the Stratix™
FPGA family powers complex designs to new levels of system integration.
Altera has rapidly rolled out Stratix devices since May 2002, and is shipping
all seven device densities in production. Customers ready to ramp their
system-on-a-programmable-chip (SOPC) designs in production have immediate
access to production versions of the high-performance Stratix devices
through Altera's distribution channels.
The rapid deployment of next-generation systems has been accompanied by a dramatic increase in demand for total FPGA bandwidth, in being restricted to non-critical peripheral processes, Stratix devices can be used at the heart of these high-bandwidth systems to accelerate performance and enable new functionality.
The Stratix device family is based on a 1.5-V, 0.13-£gm, all-layer-copper process technology and offers up to 79,040 logic elements (LEs), 7 Mbits of embedded memory, optimized digital signal processing (DSP) blocks, and high-performance I/O capabilities. Stratix devices are the ideal solution for complex, high-performance systems.
Stratix devices have a rich set of advanced features, including:
- A high-performance architecture that accelerates block-based designs for maximum system performance
- Abundant TriMatrix™ memory resources for on-chip storage
- High-bandwidth DSP blocks for signal processing-intensive applications
- Proven differential I/O technology featuring the True-LVDS™ circuitry, capable of 840-Mbps performance
- Robust clock management and frequency synthesis for managing on- and off-chip timing to maximize system performance using full-featured, embedded phase-locked loops (PLLs)
- Maximized signal quality and data transfer reliability with Terminator™ technology for differential and single-ended I/O standards
The Stratix architecture has also been designed to maximize the performance benefits of the Nios embedded processor. The advanced architectural features of Stratix devices combined with the enhanced Nios embedded processor improve the overall system performance of the soft embedded core processor to over 150 MHz, offering unparalleled processing power that meets the needs of high-bandwidth systems.
When used in conjunction with an extensive intellectual property (IP) core portfolio and the easy-to-use Quartus II development software, users can rapidly implement their high-bandwidth designs while minimizing time-to-market.
System designers that require a low-risk cost-reduction path for high-volume production can migrate their Stratix designs to HardCopy™ devices. HardCopy devices preserve the functionality and timing of the design, providing a time-saving alternative to ASICs for high-volume production.
Find answers to common questions about Stratix devices on the Questions & Answers page. Also, see what customers are saying about the new Stratix device family.
Stratix Device Family Advanced Features
Stratix devices offer features that accelerate SOPC design, increase bandwidth, and decrease time-to-market:
High-Performance Architecture: For simplifying block-based designs
- 50% average push-button performance acceleration
- Fast, continuous MultiTrack™ interconnect featuring DirectDriv™ technology
- Global and local clock resources providing up to 40 unique system clocks per device
TriMatrix Memory: Three sizes of memory blocks for various functions
- Up to 7 Mbits of embedded memory
- Multiple block sizes: 512 bits, 4 Kbits, and 512 Kbits, plus parity bits
- Up to 8 terabits per second of total memory bandwidth
- Parity bits for error checking
- Mixed-width data and mixed-width clock modes
- Embedded shift register functionality
DSP Blocks: High data throughput necessary for computationally demanding applications
- Up to 22 high-performance DSP blocks per device
- Dedicated multiplier, pipeline, and accumulation circuitry
- Predictable 300-MHz performance which provides data throughput performance of up to 2.4 giga multiply-accumulate operations per second (GMACS) per DSP block
High-Bandwidth I/O Standards & High-Speed Interfaces: Offer industry-leading high-speed differential I/O interface support
- Supports the True-LVDS solution for the LVDS, PCML, LVPECL, and HyperTransport™ high-speed differential I/O electrical standards
- Up to 152 channels per device, 80 of which are optimized for 840-Mbps performance
- Multiple instantiations of bus transfer protocols such as:
- SPI-4 Phase 2 (POS-PHY Level 4)
- 10-Gigabit Ethernet XSBI Interface (16-bit)
- HyperTransport
- RapidIO™ (Parallel)
- Common switch interface (CSIX)
- UTOPIA IV
- Support for interfaces to high-speed external
memory devices including:
- DDR and SDR SDRAM
- ZBT, QDR, QDRII, and DDR SRAM
- DDR FCRAM
PLLs for System Clock Management: Full-featured PLLs for system timing management
- Up to 12 PLLs and 40 clock networks per device
- Enhanced frequency
synthesis capabilities such as:
- Multiplication
- Division
- Phase and delay shift
- High-frequency clock generation for high-speed differential signaling
- Spread-spectrum clocking for reduced electromagnetic interference (EMI) emissions
- Dynamic PLL reconfiguration allowing on-the-fly PLL parameter changes
- Redundant clock switchover for error recovery and multi-clock systems
Terminator Technology: On-chip termination resistor technology and driver impedance matching
- Differential, parallel, and serial on-chip termination resistors
- Eliminates numerous discrete termination resistors, improves signal integrity, and reduces printed circuit board (PCB) design complexity
Device Configuration & Remote System Upgrades: Convenient system upgrades
- Remote system upgrade feature ensures the reliable and safe deployment of system upgrades and bug fixes
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